VHDL

VHDL — the VHSIC Hardware Description Language — is one of the two languages in which most of the world’s digital hardware has been designed. Like its great rival Verilog, a VHDL “program” describes not software but circuits: entities with ports, signals connecting them, and concurrent processes that model gates and clocked registers. A simulator can execute the description to verify its behavior, and a synthesis tool can compile it into real logic on an FPGA or ASIC. VHDL’s origins could hardly be more different from Verilog’s startup story: it was commissioned by the U.S. Department of Defense in 1983 as part of the Very High Speed Integrated Circuit (VHSIC) program, modeled deliberately on Ada, and pushed into the open as IEEE Standard 1076 in 1987 — years before Verilog escaped proprietary ownership. Verbose, strongly typed, and rigorously defined, VHDL became the HDL of choice in Europe, aerospace, and defense, and it remains in active use and active standardization — most recently as IEEE 1076-2019 — more than four decades on.

History and Origins

By the early 1980s the Department of Defense had a documentation crisis. Military systems were filling up with application-specific integrated circuits (ASICs), each described by a pile of vendor-specific schematics and prose that would be obsolete or unintelligible by the time the hardware needed maintenance decades later. The VHSIC program — a DoD initiative to push the state of the art in integrated circuits — needed a single, precise, executable way to document what a chip did, independent of who made it or what tools they used.

The answer was to commission a language. In July 1983, the contract to develop the VHSIC Hardware Description Language was awarded to a team of Intermetrics, IBM, and Texas Instruments. Unusually for a defense project, development was conducted in the open, with public review shaping versions 1 through 7.1. The final version produced under government contract, VHDL 7.2, was released in August 1985.

The language’s DNA was equally a product of its patron: the DoD had recently standardized on Ada for software, and VHDL borrowed Ada’s syntax, strong typing, and package system wholesale. Where Verilog would look like C, VHDL looked — and still looks — like Ada.

What happened next proved decisive. In March 1986 the DoD handed the language to the IEEE, which formed the VHDL Analysis and Standardization Group and, in December 1987, ratified IEEE Standard 1076-1987. VHDL was thus an open, vendor-neutral standard at a time when Verilog was still tied to one company’s simulator. The DoD reinforced adoption contractually: through Requirement 64 of MIL-STD-454, suppliers of ASICs to the Department of Defense were required to deliver VHDL descriptions of their parts. It was VHDL’s open-standard momentum that pressured Cadence into opening Verilog in 1990 — a rivalry that shaped the entire electronic design automation industry.

Design Philosophy

VHDL’s character follows directly from its mission — precise, tool-independent documentation of hardware:

• Ada heritage. Syntax, strong typing, packages, and general verbosity all come from Ada. Code states its intent explicitly: an entity’s interface is declared separately from its implementation (architecture), and nothing is converted between types silently.
• Strong, extensible typing. Signals, variables, and constants are strictly typed, and designers define their own types — enumerations for state machines, records for buses, constrained arrays for datapaths. Errors that Verilog’s permissiveness lets through are caught at analysis time in VHDL.
• Everything runs concurrently. A VHDL architecture is a set of concurrent statements and processes, all executing simultaneously under an event-driven simulation model — the mental shift every software programmer must make when describing hardware.
• Nine-valued logic. The IEEE 1164 std_logic type models not just 0 and 1 but unknowns, high impedance, weak drives, and don’t-cares, with resolution rules for multiple drivers — letting simulation faithfully capture bus contention and uninitialized hardware.
• Separation of interface and implementation. One entity can have several architectures — a behavioral model for fast simulation, an RTL version for synthesis, a gate-level version for sign-off — selected by configuration without touching the rest of the design.
• Simulation semantics first. Like Verilog, VHDL was defined by what a simulator should do; the synthesizable subset that tools can turn into gates is a discipline learned on top of the language.

Key Features

The entity/architecture split is visible even in “Hello, World!”, which in VHDL is a simulation-only construct — real designs describe circuits, not console output:

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entity hello is
end entity hello;

architecture sim of hello is
begin
  process is
  begin
    report "Hello, World!";
    wait;
  end process;
end architecture sim;

A synthesizable clocked counter shows the idiom at the heart of real designs — strong types, explicit conversions, and a process triggered by the clock edge:

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter is
  port (
    clk   : in  std_logic;
    reset : in  std_logic;
    count : out std_logic_vector(7 downto 0)
  );
end entity counter;

architecture rtl of counter is
  signal count_reg : unsigned(7 downto 0) := (others => '0');
begin
  process (clk) is
  begin
    if rising_edge(clk) then
      if reset = '1' then
        count_reg <= (others => '0');
      else
        count_reg <= count_reg + 1;
      end if;
    end if;
  end process;

  count <= std_logic_vector(count_reg);
end architecture rtl;

Highlights of the language include:

• Entities and architectures: a design unit’s interface (ports and generics) is declared once; multiple interchangeable implementations can be bound to it
• Signals vs. variables: signals model wires and registers with scheduled, delta-delayed updates; variables update immediately within a process — a distinction central to correct hardware modeling
• Generics and generate: compile-time parameters (bus widths, depths) and replicated or conditional structure, enabling reusable, parameterized components
• Packages and libraries: shared types, constants, and functions organized Ada-style, including the ubiquitous ieee.std_logic_1164 and ieee.numeric_std
• User-defined and resolved types: enumerations, records, physical types with units, and resolution functions governing multiply-driven signals
• Assertions and report: built-in checks that fire during simulation, extended in modern revisions by integration with the Property Specification Language (PSL)
• Testbench strength: file I/O, unconstrained arrays, and rich sequential constructs make VHDL a capable language for writing the tests that verify a design, not just the design itself

Evolution

IEEE 1076-1987 froze the DoD-era language. IEEE 1076-1993 was the first significant modernization, loosening syntax and improving consistency; the same era’s IEEE 1164 standard gave the community the shared nine-valued std_logic type that virtually all practical VHDL has been written against since. Minor revisions followed in 2000 and 2002, and IEEE 1076.1-1999 extended the language into analog and mixed-signal territory as VHDL-AMS.

The organizational landscape shifted in 2000, when VHDL International merged with its counterpart Open Verilog International to form Accellera, ending the era of competing standards bodies for the two rival HDLs.

VHDL-2008 (IEEE 1076-2008) was the biggest revision in the language’s history to that point: simplified conditional expressions, enhanced generics (including type and package generics), new fixed-point and floating-point packages, hierarchical signal access for verification, and embedded PSL assertions. Tool support arrived slowly — for years “does it support VHDL-2008?” was a standard question about any simulator — but the revision eventually became the working dialect of much of the community. The current standard, IEEE 1076-2019, approved in September 2019, continued the trajectory: driven this time largely by the user community rather than EDA vendors, it added interfaces (mode views for record ports), conditional analysis tool directives, enhanced file I/O, and a long list of language refinements aimed at verification productivity.

Current Relevance

VHDL remains one of the two working languages of digital design. In FPGA development it is fully supported as a primary input language by AMD’s Vivado and Intel’s Quartus toolchains, and it retains particular strength in Europe, where it has traditionally been the dominant HDL in industry, academia, and research institutions. In aerospace, defense, and other safety-critical fields, the same explicitness and strong typing that made Ada attractive keep VHDL in favor — the European Space Agency’s LEON fault-tolerant SPARC processors and the surrounding GRLIB IP library, deployed aboard spacecraft, are written in portable synthesizable VHDL precisely so one codebase can target radiation-hardened ASICs and commercial FPGAs alike.

The open-source ecosystem is active. GHDL provides a free simulator with full support for the 1987, 1993, and 2002 revisions of the standard and partial support for 2008 and 2019, and publishes ready-to-use Docker images; frameworks such as VUnit and OSVVM bring modern automated-testing practice to VHDL verification; and open hardware projects like the NEORV32 RISC-V system-on-chip demonstrate that a complete, production-quality processor can be written in clean, platform-independent VHDL. Broadly, industry verification has consolidated around SystemVerilog while VHDL holds strong on the design side in its home markets — a division of labor rather than a decline.

Why It Matters

VHDL’s deepest contribution is shared with Verilog: the idea that hardware could be written — described in text, simulated like a program, and compiled into gates — which made million-gate and then billion-transistor chips designable at all. But VHDL adds its own lessons to that story. It demonstrated that a government documentation requirement could produce a living engineering language: a project begun to keep DoD paperwork legible became the tool an entire continent designs chips with. Its early, open IEEE standardization forced the proprietary Verilog into the open, establishing the vendor-neutral-standard model the EDA industry still runs on. And its Ada-derived discipline — strong types, explicit interfaces, separation of specification from implementation — has kept it the language of choice wherever hardware absolutely must not fail, from military electronics to processors orbiting far beyond the reach of any repair technician.