Verilog

Verilog is a hardware description language (HDL) — a language whose programs describe not software but circuits: gates, registers, wires, and the clocked logic between them. Alongside its rival VHDL, it is one of the two languages in which most of the world’s digital silicon has been designed. A Verilog “program” is a model of hardware that a simulator can execute to verify behavior and a synthesis tool can compile into actual gates on an ASIC or FPGA. Created in the winter of 1983–84 at Gateway Design Automation and standardized as IEEE 1364, Verilog was deliberately given a C-like syntax at a time when its competitors looked like Ada — a choice that helped it win the loyalty of working chip designers. Since 2009 it has lived on as the core of SystemVerilog (IEEE 1800), the unified design-and-verification language that dominates the semiconductor industry today.

History and Origins

In 1983, Prabhu Goel — an IBM veteran known for the PODEM test-generation algorithm — founded a startup called Automated Integrated Design Systems, soon renamed Gateway Design Automation, in Massachusetts. He recruited Phil Moorby, who had worked on the HILO hardware simulation languages at Brunel University in England, to design a new modeling language and simulator. Working with Chi-Lai Huang during the winter of 1983–84, Moorby specified the language that became Verilog — the name a blend of verification and logic.

The timing was shrewd. The mid-1980s were the era when gate-level schematic capture was collapsing under the growing size of chip designs, and the industry needed to move up a level of abstraction. Verilog let engineers describe hardware behaviorally — as processes triggered by clock edges — while still supporting structural, gate-by-gate description in the same language. Moorby wrote the first Verilog simulator, which reached the market in 1985. By 1987 he had produced Verilog-XL, a dramatically faster simulator whose gate-level performance made it the de facto standard for ASIC sign-off — the simulation a design had to pass before a foundry would accept it for fabrication. For years, the language and the simulator were effectively one proprietary product: to write Verilog was to buy Gateway’s tools.

Two events at the turn of the decade changed everything. Cadence Design Systems acquired Gateway in late 1989, taking ownership of both the language and Verilog-XL. Then, in 1990, facing the rise of VHDL — a U.S. Department of Defense–sponsored language that had already become an open IEEE standard (IEEE 1076-1987) — Cadence made the pivotal decision to open Verilog to the public. Open Verilog International (OVI) was formed to steward the specification, and the newly open language was submitted to the IEEE, becoming IEEE Standard 1364-1995, known as Verilog-95.

Design Philosophy

Verilog’s design reflects the realities of hardware, filtered through a deliberately familiar surface:

• C-flavored syntax. Operators, expressions, and much of the flavor of Verilog come straight from C (with visible traces of Pascal and Fortran, and of the HILO simulation languages Moorby had worked on). Where VHDL demanded Ada-style verbosity and strong typing, Verilog let engineers write terse, permissive code — a trade-off practicing designers largely embraced.
• Everything runs concurrently. Hardware is inherently parallel, so a Verilog module is a collection of processes (always and initial blocks) and continuous assignments that all execute simultaneously, coordinated by an event-driven simulation scheduler. This is the deepest mental shift for software programmers: statements do not run top to bottom; blocks run whenever their triggering events fire.
• Four-valued logic. Signals are not just 0 and 1 but also X (unknown) and Z (high-impedance), letting simulations model uninitialized registers, bus contention, and tri-state buses faithfully.
• One language, many abstraction levels. The same design can be described behaviorally (algorithms and clocked processes), at the dataflow level (continuous assignments), structurally (instantiated gates and modules), or as a mixture — and refined from one level to another as it moves toward silicon.
• Simulation semantics first. Verilog was specified by what a simulator should do. The synthesizable subset — the portion tools can turn into real gates — was a discipline layered on afterward, which is why every Verilog designer learns the difference between code that simulates and code that can be built.

Key Features

A Verilog module is the unit of design — a black box with ports, containing logic. Even “Hello, World!” reveals the event-driven model:

1
2
3
4
5
6

module hello;
  initial begin
    $display("Hello, World!");
    $finish;
  end
endmodule

Real designs describe clocked hardware. This synthesizable counter shows the idiom at the heart of nearly every digital chip:

 1
 2
 3
 4
 5
 6
 7
 8
 9
10
11
12

module counter (
  input  wire       clk,
  input  wire       reset,
  output reg  [7:0] count
);
  always @(posedge clk) begin
    if (reset)
      count <= 8'd0;          // non-blocking assignment: all registers
    else                      // update together at the clock edge
      count <= count + 8'd1;
  end
endmodule

Highlights of the language include:

• Modules and hierarchy: designs compose by instantiating modules inside modules, mirroring the physical hierarchy of a chip
• Nets and registers: wire types model physical connections driven by continuous assignments; reg types hold values assigned in procedural blocks
• Blocking (=) vs. non-blocking (<=) assignment: the distinction that models combinational logic versus clocked registers — and the source of the language’s most famous beginner bugs
• Bit-level precision: arbitrary-width vectors ([31:0]), part-selects, concatenation ({a, b}), and replication operators for describing datapaths exactly
• Delays and timing: # delays and timing checks for modeling real gate and interconnect behavior in simulation
• System tasks and functions: $display, $monitor, $dumpvars, $readmemh and friends for testbench I/O and waveform generation
• Generate constructs (since Verilog-2001): compile-time elaboration of repetitive or parameterized structure, such as instantiating N copies of a block
• PLI/VPI programming interfaces: C-language hooks that let external code interact with a running simulation

Evolution

Verilog-95 (IEEE 1364-1995) froze the language essentially as Gateway had built it. The first real modernization came with Verilog-2001 (IEEE 1364-2001), the revision most working engineers still recognize as “classic Verilog”: generate blocks, signed arithmetic, ANSI-style port declarations, and the always @* shorthand for combinational sensitivity lists. Verilog-2005 (IEEE 1364-2005) added minor corrections and small features such as the uwire keyword.

By then the action had moved to SystemVerilog. Verification — proving a chip correct before committing millions of dollars to masks — had outgrown plain Verilog, and engineers were bolting on external languages for testbenches. SystemVerilog, standardized as IEEE 1800-2005, extended Verilog with classes, constrained-random stimulus, assertions, coverage constructs, and richer types, unifying design and verification in one language. In 2009 the two standards formally merged as IEEE 1800-2009: Verilog ceased to exist as a separate standard and became the design-oriented core of SystemVerilog. The merged standard has been revised in 2012, 2017, and most recently IEEE 1800-2023, approved in December 2023. A separate Accellera standard, Verilog-AMS, extends the language into analog and mixed-signal modeling.

Current Relevance

Calling Verilog a legacy language would be exactly wrong — it simply answers to a new name. The synthesizable heart of nearly every SystemVerilog design is Verilog, and enormous quantities of plain Verilog-2001-style RTL are written, maintained, and fabricated every year. In the commercial world, the big three EDA vendors — Synopsys, Cadence, and Siemens EDA — all support the language family in their simulators and synthesis tools, and FPGA designers use it daily in AMD’s Vivado and Intel’s Quartus toolchains.

Verilog is also the lingua franca of the open-source hardware movement. Icarus Verilog provides a free IEEE-1364 simulator; Verilator compiles synthesizable Verilog into fast C++ models and has become a cornerstone of large-scale open simulation; Yosys performs open-source synthesis from Verilog, anchoring fully open ASIC flows such as OpenLane targeting the SkyWater open PDK. The RISC-V ecosystem, much of it developed in the open, has poured fresh energy into Verilog-family tooling. Meanwhile, newer hardware construction languages such as Chisel and Amaranth do not replace Verilog so much as generate it — Verilog remains the interchange format the entire toolchain understands.

Why It Matters

Verilog’s deepest contribution is the idea it embodied: that hardware could be written — described in a text language, simulated like a program, and compiled into gates — rather than drawn. Together with VHDL, it powered the register-transfer-level methodology that made million-gate and then billion-transistor chips designable at all; the smartphone, the GPU, and the datacenter are all downstream of that abstraction. Its history is also a classic study in open standards: as a proprietary language wedded to one company’s simulator, Verilog was on track to lose to the openly standardized VHDL, and it was Cadence’s 1990 decision to give the language away that secured its dominance in the ASIC world. And its C-like pragmatism — permissive typing, terse syntax, simulation-first semantics — set the cultural tone for the hardware design languages that followed, up to and including the SystemVerilog that carries it, invisibly and indispensably, inside virtually every chip designed today.