HERA

HERA (the Haverford Educational RISC Architecture) is a 16-bit instruction set and assembly language designed by David G. Wonnacott for Haverford College’s undergraduate computer science curriculum. The architecture is used across four upper-level courses. Students learn assembly programming in HERA, write compilers that emit HERA code, build a HERA processor from logic gates, and then extend that processor to support an operating system. The result is a single system that the same students build “from the level of single-bit AND, OR, and NOT gates up through a high-level language,” as the project’s home page puts it.

History & Origins

According to the prologue of the official guide, HERA “originated with an attempt to adapt Andrew Appel’s ‘Jouette’” for use in a Computer Hardware course based on M. Morris Mano’s Computer Engineering: Hardware Design (1988). Jouette is the simplified instruction set Appel uses to illustrate instruction selection in Modern Compiler Implementation (1998).

Wonnacott’s HERA page says the Version 1.0 processor was “developed and used from 2000 through the spring of 2003.” One early reference survives: a four-page sheet titled HERA Architecture and Assembly Language (version 0.99), whose PDF is dated May 2002. It describes a somewhat different machine from today’s. It counted seventeen 16-bit registers, including the program counter and a dedicated Old Frame Pointer (OFP) in register 13, and its branch instructions (BR, BRN, BR2) named flag numbers directly. Wonnacott credits Todd Miller (Haverford class of 2001) with significant work on the early C++ macros that became HERA-C.

Version 2 replaced Version 1.0 after spring 2003. Wonnacott presented the system in a poster session at SIGCSE ‘05 and then in the peer-reviewed paper Unifying the undergraduate applied CS curriculum around a simplified microprocessor architecture, given at the 22nd Annual Consortium for Computing Sciences in Colleges Eastern Conference (CCSC-E ‘06) in October 2006. The encyclopedia’s master list gives HERA’s year as 2006, which is the year of that paper. The language itself had been in classroom use since 2000.

Design Philosophy

HERA is built to sit at a deliberately chosen point between toy and real machines. The guide describes the instruction set as “powerful enough to illustrate assembly-language programming techniques and serve as a target for compilers, yet simple enough to be implemented as a student project.”

Three ideas shape the design:

• One architecture, four courses. Students reuse the same machine and toolchain from course to course instead of learning a new simulator each time. The HERA page says this “minimizes the overhead of introducing new architectures or simulation tools.”
• A small RISC core with assembler idioms built on top. Like real RISC designs, HERA leaves out hardware for anything a short instruction sequence can do. There is no hardware MOVE (an OR with the zero register does the job), no bit-wise NOT (an XOR with 0xffff does it), and no compare instruction (a SUB into R0 sets the flags and throws away the result). The assembler supplies these as standard pseudo-operations.
• Familiar tools. The HERA-C system lets students run and debug HERA programs inside an ordinary C/C++ development environment. Students can run assembly code long before their own processor works.

Wonnacott contrasts HERA with two other teaching designs. Nisan and Schocken’s The Elements of Computing Systems uses a “much simpler” register/memory processor, while HERA is register/register. Patt and Patel’s Introduction to Computing Systems uses an architecture “considerably simpler than HERA.” He places RISC-V at the opposite end of the scale.

Key Features

Machine Model (Version 2.4)

The carry-block flag is unusual. According to the guide, it is “not found on most processors.” When it is set, ADD, SUB and MUL ignore the incoming carry and behave like ordinary single-precision operations. When it is clear, the same instructions chain the carry from one word to the next, which is how HERA code does multi-word arithmetic. MUL goes further: with carry-block clear, the other flags select the result, giving the low 16 bits of the product when all are clear and the high 16 bits of the signed product when only s is set. The guide leaves the remaining fourteen flag combinations undefined.

Instruction Groups

• Constants: SETLO loads a sign-extended 8-bit value and SETHI sets the high byte. The SET pseudo-op combines the two to load any 16-bit value.
• Three-address arithmetic and logic: ADD, SUB, MUL, AND, OR, XOR.
• Immediate increment/decrement: INC and DEC take values from 1 to 64.
• Shifts: LSL, LSR, LSL8, LSR8, ASL, ASR.
• Flag manipulation: SAVEF, RSTRF, FON, FOFF, FSET4, FSET5.
• Memory: LOAD and STORE.
• Control flow: fifteen branch types (unconditional BR plus fourteen conditions, with the sixteenth opcode slot unused), each available as a register-mode branch (BZ) and a relative branch (BZR). There are also CALL and RETURN, plus SWI and RTI, which are reserved for interrupt processing.

HALT and NOP are not separate instructions. They are relative branches by 0 and by 1. The guide gives a worked encoding: the pseudo-op CMP(2,3) assembles to 0x3068 0xB023, which sets the carry flag and then subtracts R3 from R2 into R0.

Assembly Syntax

HERA source looks like a series of C function calls. This follows from HERA-C, which implements each instruction as a C++ macro. Labels, data statements and C-style comments are supported:

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// Sum the integers 10 down to 1 into R1
CBON()              // carry-block on: plain single-precision arithmetic
SET(R1, 0)          // running total
SET(R2, 10)         // loop counter
LABEL(loop)
ADD(R1, R1, R2)
DEC(R2, 1)          // sets the zero flag when R2 reaches 0
BNZR(loop)          // relative branch back while R2 != 0
HALT()

Part II of the guide covers HERA idioms in detail: double-precision arithmetic, length-prefixed arrays, Tiger-style strings, records, stack frames, and both “caller-save” (parameters in registers) and “callee-save” (parameters on the stack) calling conventions.

Tooling

hera-py’s README describes the trade-offs between the tools. hera-py adds features HERA-C lacks, such as stack-overflow detection and branching by register value. HERA-C supports C #define macros and arbitrary embedded C++, which hera-py does not.

Evolution

• Version 1.0 (2000-2003): the original processor, adapted from Jouette. The surviving 0.99 sheet (May 2002) already has the zero register and carry-block flag, but reserves register 13 as an Old Frame Pointer and uses flag-numbered branches.
• Version 2 (from 2003): the current architecture, documented in a guide written with TeXmacs. It has fifteen named branches (one unconditional, fourteen conditional), each in register and relative form, and conventional roles for R11-R13 in place of the Old Frame Pointer.
• Version 2.4.0 (October 2018): the latest published specification. A printed edition was also sold through lulu.com, with the quick reference on the back cover.

By 2020 Wonnacott wrote that the specification “has been relatively stable for some years, and meets our current curricular needs.” He expected future changes to be “minor clarifications to the documentation, and bug fixes for tools.”

Current Relevance

HERA has never been used outside the Haverford curriculum and the student projects connected to it. Fisher’s May 2020 write-up of hera-py notes that the full PDF reference had at one point “evidently gone missing” from Haverford’s website. Web-archive captures from 2025 show the Version 2.4.0 guide and quick reference still being served from Haverford’s computer science pages. Student repositories on GitHub include Tiger compilers that target HERA and an experiment putting HERA on a TinyFPGA BX board. These suggest the architecture was still being taught into the early 2020s. Whether it is still used in Haverford’s courses today has not been confirmed.

Why It Matters

HERA shows a different way to teach systems. Many curricula use a separate teaching machine in each course, or squeeze the whole stack into one semester. Haverford instead spreads a single, moderately realistic RISC design across four courses. Students write the assembly, generate it with their own compilers, run it on a CPU they designed, and drive a terminal with device drivers they wrote. The design keeps real RISC habits: a zero register, pseudo-instructions in place of hardware conveniences, and separate signed and unsigned branch conditions. It stays small enough that an undergraduate can build the whole processor. That combination has kept it in use at Haverford for at least two decades.