CUPL

CUPL — Compiler for Universal Programmable Logic — is a hardware description language and compiler designed for programming Programmable Logic Devices (PLDs). Released in 1983 by Assisted Technology, Inc., CUPL is widely regarded as the first commercial PLD design tool that could target devices from multiple manufacturers using a single language. Before CUPL, tools like PALASM were tied to specific device families from specific vendors. CUPL broke that limitation, allowing engineers to describe logic once and compile it to fuse maps for PALs, GALs, CPLDs, and other programmable devices across vendors.

History and Origins

CUPL was released in 1983 by Assisted Technology, Inc. for the IBM PC running MS-DOS. The software was written in C for portability — a notable choice at a time when many similar tools were written in FORTRAN. While the name expands to “Compiler for Universal Programmable Logic,” the software was generally referred to simply as “CUPL” rather than by its full acronym.

The timing was significant. Monolithic Memories, Inc. (MMI) had introduced the Programmable Array Logic (PAL) architecture in 1978, and by the early 1980s multiple vendors — AMD, National Semiconductor, Lattice Semiconductor, and others — were producing compatible PLD devices. MMI offered PALASM, its own design tool, but PALASM only targeted MMI’s PAL devices. CUPL filled a real gap: engineers working with PLDs from different vendors needed a tool that could target all of them.

In July 1985, Assisted Technology was acquired by Personal CAD Systems (P-CAD), a company based in Los Gatos, California that specialized in electronic design automation. P-CAD integrated its schematic capture tools as a front end for CUPL. P-CAD itself was later acquired by Cadam (a Lockheed subsidiary) in 1989. Through a series of corporate transitions, the CUPL intellectual property reportedly passed to Logical Devices, Inc., which published reference materials and continued development.

Meanwhile, Atmel Corporation developed WinCUPL, a free Windows-based version of the CUPL compiler, to support its line of PLD products including the popular ATF16V8, ATF22V10, and ATF1500-series devices. When Microchip Technology acquired Atmel in 2016, WinCUPL came along with the PLD product line. Microchip continues to distribute WinCUPL as a free tool, and in August 2025 released WinCUPL II to address compatibility issues with modern Windows versions.

Design Philosophy

CUPL’s core design principle is device independence. A designer writes logic descriptions using symbolic names and Boolean expressions without concern for the specifics of the target device’s internal architecture or fuse patterns. The CUPL compiler handles the translation from abstract logic to the physical fuse map (in JEDEC format) needed to program the device.

Key design principles include:

• Pin polarity transparency: Designers can declare signals as active-high or active-low in pin definitions, and the compiler automatically handles all polarity transformations. Logic equations are written without worrying about physical pin polarity.
• Multiple design entry paradigms: CUPL supports Boolean equations, truth tables, and state machine descriptions, allowing the designer to use whichever representation best fits the problem at hand.
• Simulation and verification: Test vectors can be specified within CUPL source files, enabling functional simulation before committing a design to silicon.

Key Features

Boolean Equations

The primary design entry method in CUPL uses Boolean operators with a concise syntax:

!   NOT
&   AND
#   OR
$   XOR

Operator precedence follows: NOT > AND > OR > XOR.

output = (a & b) # (!c & d);

Pin and Node Declarations

CUPL maps symbolic variable names to physical device pins and supports internal nodes for intermediate signals:

Pin 1 = clock;
Pin 2 = input_a;
Pin 3 = input_b;
Pin 14 = !output;    /* active-low output */

Bit Fields

The FIELD keyword groups related signals for cleaner code:

FIELD address = [A3..A0];
FIELD data = [D7..D0];

Truth Tables

For combinational logic that is more naturally expressed as input/output mappings:

TABLE input_a, input_b => output;
  'b'00 => 'b'0;
  'b'01 => 'b'1;
  'b'10 => 'b'1;
  'b'11 => 'b'0;

State Machine Descriptions

Sequential logic is described using SEQUENCE blocks with PRESENT, IF, DEFAULT, and OUT statements:

SEQUENCE state_reg {
    PRESENT S0
        IF input NEXT S1;
        DEFAULT NEXT S0;
    PRESENT S1
        OUT enable;
        IF input NEXT S1;
        DEFAULT NEXT S0;
}

Number Formats

CUPL supports multiple number bases — binary ('b'), octal ('o'), decimal ('d'), and hexadecimal ('h') — with don’t-care values ('X') supported in truth tables.

Simulation and Test Vectors

Test vectors can be included directly in the source file using a structured format. Special symbols include C (clock pulse), L and H (expected output low/high), and Z (high-impedance).

Program Structure

A CUPL source file (.pld extension) follows a defined structure:

Name     AddressDecoder;
Partno   001;
Date     04/06/2026;
Revision 01;
Designer Engineer;
Company  Example;
Assembly None;
Location None;
Device   g16v8a;

/* Pin Declarations */
Pin 1 = A15;
Pin 2 = A14;
Pin 3 = A13;
Pin 19 = !ROM_CS;
Pin 18 = !RAM_CS;
Pin 17 = !IO_CS;

/* Logic Equations */
ROM_CS = A15 & A14;
RAM_CS = !A15;
IO_CS = A15 & !A14 & A13;

The header section with Name, Partno, Date, and other metadata fields is required. The Device field specifies the target PLD, and the compiler uses this to validate that the design fits within the device’s capabilities.

Supported Devices

CUPL has supported devices from numerous manufacturers over its history:

• Simple PLDs (SPLDs): PALs and GALs from AMD, Lattice, Atmel, National Semiconductor, and others
• Complex PLDs (CPLDs): Atmel ATF1500 and ATF1508 series, among others
• FPGAs: The commercial “CUPL Total Designer” package supported devices from Altera, Xilinx, and others

The current WinCUPL distribution from Microchip primarily targets Atmel-branded devices including the ATF16V8C, ATF20V8, ATF22V10C, ATF750C, and ATF1502/1504/1508 CPLDs. For simple SPLDs, CUPL generates the JEDEC fuse map directly. For ATF150x-series CPLDs, an additional fitter (place-and-route) stage is required.

Evolution

CUPL’s evolution has been shaped less by language changes and more by the changing landscape of the PLD industry:

• 1983-1985: Original MS-DOS version established CUPL as the leading third-party PLD design tool
• Late 1980s-1990s: The rise of CPLDs and FPGAs expanded the range of target devices; the CUPL Total Designer package added schematic capture, graphical state machine editing, and support for output to EDIF, VHDL, Verilog, and other formats
• Late 1990s-2000s: As FPGA design shifted toward Verilog and VHDL, CUPL’s role narrowed to smaller PLDs where a full HDL synthesis flow was unnecessary
• 2010s-present: CUPL persists as the standard tool for Atmel/Microchip SPLDs and small CPLDs, which remain among the few 5V programmable logic devices still in active production

The CUPL language syntax itself has remained remarkably stable over four decades, which is both a strength (existing designs still compile) and a reflection of the maturity of the simple PLD design problem it addresses.

Current Relevance

CUPL occupies a narrow but persistent niche. Microchip’s Atmel-branded GALs (ATF16V8, ATF22V10) are among the last 5V programmable logic devices still manufactured, and CUPL via WinCUPL remains the primary free design tool for these parts. The release of WinCUPL II in 2025, specifically to address Windows 10/11 compatibility, demonstrates that Microchip considers ongoing tool support worthwhile for this product line.

The hobbyist and retrocomputing communities have given CUPL a second life. Designers building custom address decoders, bus interfaces, and glue logic for retro hardware projects frequently use CUPL with ATF-series GALs. Resources including community-maintained GitHub repositories and tutorials continue to appear.

In professional contexts, simple PLDs programmed with CUPL still appear in designs where a small amount of 5V glue logic is needed and an FPGA would be excessive — industrial control, legacy system maintenance, and embedded applications with 5V bus requirements.

Why It Matters

CUPL’s historical significance lies in establishing the principle of device-independent hardware description for programmable logic. Before CUPL, each PLD vendor provided its own proprietary design tool. CUPL demonstrated that a single language and compiler could target devices from multiple manufacturers, giving designers freedom to choose components based on technical merit rather than tool availability. This same principle — write once, target many devices — later became fundamental to the success of Verilog and VHDL in the FPGA era.

CUPL also represents one of the earliest examples of a domain-specific language for hardware design that achieved widespread commercial adoption, with Assisted Technology’s marketing materials from the era claiming support for over 30,000 design engineers. Its longevity — still in active use over four decades after its introduction — speaks to the enduring value of simple, well-targeted tools that solve a specific problem well.