Assembler (PowerPC)

Assembler (PowerPC) is the assembly language for the PowerPC instruction set architecture, created by the Apple-IBM-Motorola alliance in the early 1990s as a single-chip, licensable distillation of IBM’s POWER architecture. It is a large, comfortable RISC: fixed 32-bit instructions and a strict load/store discipline, but with thirty-two general-purpose registers, thirty-two floating-point registers, a genuinely unusual eight-field condition register, hardware loop support, and a set of rotate-and-mask instructions rich enough that experienced programmers treat bitfield manipulation as a single-instruction operation. PowerPC assembly was the language of the Macintosh for twelve years, of the GameCube, Wii, Wii U, Xbox 360, and PlayStation 3, and — through the radiation-hardened RAD750 — it remains the assembly language currently executing on the surface of Mars. The architecture no longer drives new desktop designs, but it never disappeared: it survives inside the Power ISA specification, in IBM’s server line, and across a large installed base of embedded controllers.

History & Origins

From 801 to POWER (1975-1990)

PowerPC’s lineage begins with IBM’s 801 project at the Thomas J. Watson Research Center, started in 1975 under John Cocke. The 801 was one of the founding RISC efforts — the argument that a small set of simple, uniform instructions executed in a single cycle would outperform a rich set of complex, microcoded ones. Its ideas resurfaced commercially in POWER (Performance Optimization With Enhanced RISC), the architecture behind IBM’s RS/6000 workstations, which shipped in 1990.

POWER was fast and technically well regarded, but it was implemented as a multi-chip design and it was IBM’s alone. It was not something a personal computer could be built around, and it was not something another vendor could license.

The AIM Alliance (1991-1994)

In 1991, three companies with converging problems formed what became known as the AIM alliance. Apple needed a successor to the Motorola 68000 line, whose performance trajectory was flattening against Intel’s. IBM had an excellent architecture confined to expensive workstations. Motorola had semiconductor manufacturing and a customer base but was losing the desktop CPU race. The agreement was to produce a single-chip, cost-reduced, licensable derivative of POWER — PowerPC, sometimes expanded as “Performance Optimization With Enhanced RISC — Performance Computing.”

The engineering moved unusually quickly. On October 1, 1992, IBM and Motorola announced that the first PowerPC 601 had been designed and fabricated, with first silicon delivered later that month — roughly twelve months from project start. The 601 was a deliberate hybrid, implementing most of the new PowerPC instruction set while retaining a number of POWER1 instructions so that existing RS/6000 software would run. IBM began shipping 601-based RS/6000 workstations in October 1993, and Apple shipped the first Power Macintosh systems on March 14, 1994.

The 603 (low-power, aimed at portables) and 604 (higher performance) followed as the first designs without the POWER1 carry-overs. The 620, the first 64-bit PowerPC, arrived in the mid-1990s but saw very limited commercial adoption.

The Apple Years and the Console Years (1997-2006)

The PowerPC 750, introduced in 1997 and marketed by Apple as the G3, was the architecture’s most consequential single core. It was efficient, licensable, and endlessly re-used: it became the basis for Nintendo’s Gekko (GameCube, 2001) and Broadway (Wii, 2006), and for BAE Systems’ radiation-hardened RAD750.

The PowerPC 7400 (G4) arrived in 1999 with AltiVec, a 128-bit SIMD extension with thirty-two dedicated vector registers — a notably clean SIMD design for its era, and one that Apple marketed heavily as the “Velocity Engine.” IBM called the same extension VMX. In 2003 the PowerPC 970 (G5), derived from IBM’s server-class POWER4, brought 64-bit computing to the Macintosh desktop.

Then the alliance came apart. Motorola spun its semiconductor division out as Freescale in 2004. IBM’s PowerPC roadmap increasingly served servers and consoles rather than laptops, and the G5 in particular never reached a thermal envelope suitable for a PowerBook. In June 2005, Apple announced at WWDC that the Macintosh would move to Intel x86; the transition completed in 2006.

Console adoption ran in the opposite direction over the same years. Microsoft’s Xbox 360 (2005) used the tri-core PowerPC Xenon. Sony’s PlayStation 3 (2006) used the Cell processor, whose control core was a PowerPC PPE. For roughly a decade, essentially all mainstream home console assembly programming was PowerPC assembly programming, though handhelds of the era ran ARM and MIPS.

Opening the Architecture (2004-2019)

Power.org was founded in 2004 by IBM and fifteen other companies to steward the architecture as a licensable open standard. Its most important technical act came in September 2006 with Power ISA Version 2.03, which merged the PowerPC instruction set with the embedded-oriented Book E specification into one architecture spanning microcontrollers to servers. From that point forward “PowerPC” names a large portion of Power ISA rather than a separate architecture.

The OpenPOWER Foundation followed in 2013, founded by IBM with Google, NVIDIA, Mellanox, and Tyan to let outside parties build Power chips and systems. The same period brought the ELFv2 ABI and, from POWER8 onward, first-class little-endian Linux on POWER. In August 2019, IBM announced that the Power ISA would be available royalty-free through the OpenPOWER Foundation, which itself moved under the Linux Foundation — a direct response to the momentum RISC-V had built.

Design Philosophy

PowerPC belongs to the RISC tradition, but it is a distinctly generous RISC — closer in spirit to “make every instruction simple and fast” than to “make the instruction set as small as possible.”

Load/store, but with a large register file: Arithmetic operates only on registers, and only loads and stores touch memory. But with 32 GPRs and 32 FPRs, compilers rarely run short, and hand-written code has room to keep working sets resident.

Fixed 32-bit encoding, many formats: Every instruction is exactly 32 bits and word-aligned, which keeps decode cheap. Unlike MIPS’s three formats, PowerPC uses a couple of dozen encoding forms — decode is still simple, but the instruction set is far broader.

A condition register, not condition codes: PowerPC has a 32-bit Condition Register divided into eight independent 4-bit fields (CR0-CR7). Comparisons write into whichever field you name, so multiple independent conditions can be live at once and a branch can be scheduled well ahead of its test. This is the architecture’s most distinctive feature and its biggest departure from both x86’s single flags register and MIPS’s do-it-with-general-registers approach.

Branch resources are architectural: The Link Register (LR) holds return addresses and the Count Register (CTR) serves as a loop counter or indirect branch target. bdnz decrements CTR and branches in one instruction; bctrl performs an indirect call. Branch behavior is separated from general computation on purpose, so the branch unit can run ahead of the integer pipeline.

Bi-endian by design: PowerPC can operate big-endian or little-endian, selectable by a mode bit (the PowerPC 970 being a notable exception that dropped little-endian mode). Big-endian was the default for the Macintosh, AIX, and console era; modern Linux on POWER runs little-endian.

Fused multiply-add from day one: PowerPC included fmadd and its variants — a single-rounding multiply-then-add — decades before the equivalent reached mainstream x86. This mattered enormously for numerical and graphics code.

Key Features

Register Model

r0 is a normal register for arithmetic, but in most address computations it reads as the literal value 0 rather than its contents — a well-known trap for people writing PowerPC assembly by hand.

The 32-bit SysV ABI passes the first eight integer arguments in r3-r10 and returns in r3; r1 is the stack pointer and r2 is reserved (used as the TOC pointer in the 64-bit ABIs). The 64-bit ELFv1 ABI, used by AIX-style and big-endian Linux systems, calls through function descriptors rather than direct code addresses; ELFv2 (defined around 2013-2014) removed descriptors and is what little-endian Linux on POWER uses.

The Condition Register and Dot Forms

Most arithmetic instructions come in two forms: a plain form that leaves CR alone, and a “record” form suffixed with . that updates CR0 with the sign of the result.

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        add     r3, r4, r5      # r3 = r4 + r5, CR untouched
        add.    r3, r4, r5      # same, and CR0 records lt/gt/eq for the result
        cmpwi   cr1, r6, 0      # compare r6 with 0, result into CR1 specifically
        beq     cr1, done       # branch on CR1's eq bit

Being able to target a specific CR field is what lets a compiler hoist a comparison far away from the branch that consumes it without the two colliding.

Hardware Loop Control

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        li      r3, 100
        mtctr   r3              # move-to CTR: loop 100 times
loop:
        lwzu    r4, 4(r5)       # load word and update r5 by 4 in one instruction
        add     r6, r6, r4
        bdnz    loop            # decrement CTR, branch if nonzero

bdnz is a decrement-test-branch in a single instruction with no CR involvement, and the load-with-update forms (lwzu, stwu) fold pointer increment into the memory access. Tight array loops in PowerPC are unusually compact for a RISC.

Rotate and Mask

The rlwinm family — rotate left word immediate then AND with mask — is PowerPC’s signature instruction. One instruction covers shifts, bitfield extraction, bitfield alignment, and masking:

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        rlwinm  r3, r4, 0, 16, 31       # extract low 16 bits of r4 into r3
        rlwinm  r3, r4, 24, 0, 7        # rotate left 24, keep bits 0-7
        slwi    r3, r4, 4               # simplified mnemonic for rlwinm r3,r4,4,0,27

Assemblers provide simplified mnemonics (slwi, srwi, clrlwi, extrwi, and many more) that expand to rlwinm with computed operands. Reading real PowerPC disassembly means being fluent in both notations, since disassemblers vary in which they print.

Hello World (32-bit Linux/PowerPC)

The sc instruction traps to the kernel with the syscall number in r0 and arguments in r3 onward:

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        .section .rodata
msg:    .string "Hello, World!\n"
len     = . - msg - 1

        .text
        .globl _start
_start:
        li      0, 4            # __NR_write
        li      3, 1            # fd = stdout
        lis     4, msg@ha       # high-adjusted half of &msg
        addi    4, 4, msg@l     # plus low half
        li      5, len          # byte count
        sc

        li      0, 1            # __NR_exit
        li      3, 0
        sc

The lis + addi pair with @ha and @l relocations is how a 32-bit address is built from 16-bit immediate fields — the same two-instruction idiom every fixed-width RISC needs, and something you will see constantly in PowerPC disassembly.

Function Calls

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add3:                           # int add3(int a, int b, int c)
        add     3, 3, 4
        add     3, 3, 5
        blr                     # branch to Link Register = return

caller:
        mflr    0               # LR is not preserved across calls...
        stw     0, 4(1)         # ...so save it into the caller's frame
        stwu    1, -16(1)       # push a stack frame, storing the back-chain link
        li      3, 1
        li      4, 2
        li      5, 3
        bl      add3            # sets LR to the following instruction
        addi    1, 1, 16        # pop the frame
        lwz     0, 4(1)
        mtlr    0               # restore LR
        blr

Two things distinguish this from most other RISC calling conventions. First, bl writes the return address into the dedicated Link Register rather than a general register, and it must be explicitly saved before making a nested call. Second, stwu r1, -16(r1) both allocates the frame and writes the caller’s stack pointer into the new frame’s first word — PowerPC ABIs maintain a linked back chain of stack frames, which makes stack unwinding possible without debug information.

AltiVec / VMX

AltiVec added thirty-two architecturally separate 128-bit vector registers, operating on 16 bytes, 8 halfwords, 4 words, or 4 single-precision floats:

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        lvx     v0, r3, r4      # load 16 bytes (address forced 16-byte aligned)
        vaddubs v2, v0, v1      # add 16 unsigned bytes with saturation
        vmaddfp v3, v0, v1, v2  # 4-wide single-precision fused multiply-add
        stvx    v2, r5, r6

Loads and stores ignore the low four address bits, forcing alignment; unaligned access is handled with lvsl and vperm, an idiom that appears in essentially all hand-tuned AltiVec code. IBM later extended the concept as VSX (Vector-Scalar Extension), introduced with POWER7, which unified the floating-point and vector register files into 64 architected 128-bit registers.

Evolution

Two architectural shifts are worth calling out for anyone reading PowerPC code across eras. The first is endianness: code and data layouts from the Macintosh, AIX, and console era are big-endian, while modern Linux on POWER is little-endian, and this changes byte-order assumptions throughout. The second is the arrival of prefixed instructions in Power ISA v3.1, which for the first time allow a 32-bit prefix word ahead of a 32-bit instruction — breaking the fixed-width property that had held since 1992, in order to get larger immediates and PC-relative addressing.

Current Relevance

PowerPC assembly is not a language anyone reaches for on a new project, but the code and hardware are still very much in service:

Spaceflight. The RAD750 remains the standard radiation-hardened flight processor for NASA and other space agencies. It is aboard Curiosity, Perseverance, the Lunar Reconnaissance Orbiter, and the James Webb Space Telescope. Flight software is written mostly in C, but boot code, exception handlers, and timing-critical routines are PowerPC assembly, and mission software must be understood at that level.

Servers. IBM Power Systems running AIX, IBM i, and Linux implement Power ISA directly. Kernel, hypervisor, JIT, and cryptographic library work on these machines is done in Power assembly, and OpenPOWER makes the specification freely implementable.

Embedded and automotive. NXP’s Power Architecture microcontrollers remain in production for automotive and industrial control, where functional-safety certification often requires reviewing what the compiler actually emitted. PowerPC 4xx and e500 cores persist in networking and storage firmware, and PowerPC 405 cores were embedded in Xilinx Virtex-series FPGAs of the 2000s, parts still found in long-lived designs.

Emulation, decompilation, and reverse engineering. Dolphin (GameCube/Wii), RPCS3 (PlayStation 3), Xenia (Xbox 360), and the decompilation projects that reconstruct C source from console binaries all involve reading enormous quantities of PowerPC assembly. This is where most people encounter PowerPC assembly for the first time today.

Retrocomputing. MorphOS and AmigaOS 4 still target PowerPC, and the Mac OS 9 and early Mac OS X communities keep PowerPC toolchains alive.

Tooling remains healthy: GCC, Clang/LLVM, and GNU binutils all target 32- and 64-bit PowerPC in big- and little-endian modes; QEMU emulates PowerPC systems; and most Linux distributions package powerpc-linux-gnu cross-toolchains.

Why It Matters

PowerPC is the clearest case in computing history of a technically strong architecture that lost the desktop and then quietly outlived that loss.

Its technical contributions were real and durable. Fused multiply-add, a partitioned condition register that decouples comparison from branching, a clean and register-rich SIMD extension, and a hardware loop counter were all present and well-executed at a time when the dominant desktop architecture had eight general registers and a single flags word. Several of these ideas were eventually adopted elsewhere: x86 gained fused multiply-add with FMA3 in AMD’s Piledriver (2012) and Intel’s Haswell (2013), roughly two decades after PowerPC shipped it.

Its commercial arc is instructive in a different way. The AIM alliance was an explicit attempt by three large companies to break a monopoly by pooling architecture, manufacturing, and a captive platform. It produced excellent chips and still failed at its primary goal, because the constraint that ultimately mattered — performance per watt in a laptop — was not the one the alliance was organized around. Apple’s 2005 announcement was, in the end, a thermal decision.

And PowerPC did not actually die. It was folded into Power ISA in 2006, opened through OpenPOWER in 2013, and made royalty-free in 2019 — arriving, by a very different route, at roughly the position RISC-V occupies. Meanwhile the installed base kept running: in cars, in routers, in factory controllers, in three generations of game consoles, and in the flight computers of spacecraft that will still be executing PowerPC instructions long after the desktop argument has been forgotten.