Assembler (PA-RISC)

PA-RISC assembly is the machine language of Hewlett-Packard’s Precision Architecture, the load/store RISC design that carried HP’s Unix workstations and servers, and its older MPE-based business systems, from 1986 into the mid-2000s. It began life inside HP Laboratories under the codename Spectrum, and its instruction set shows the fingerprints of that origin: a clean, regular RISC core with a distinctive syntax feature — the comma-suffixed completer — that does the work PDP-11-descended assemblers spread across separate opcode variants and addressing modes.

History and Origins

Spectrum

By the early 1980s HP’s product lines were split across several incompatible instruction sets — stack-based systems for the HP 3000 business line, and various designs across its technical and scientific workstations. The Spectrum program, begun at HP Labs in Palo Alto around 1982, set out to replace all of them with a single scalable architecture, with design goals HP later summarized as leadership in price/performance, a migration path for existing customers, and one unified instruction set across the product range. A TTL implementation effort began in April 1983, simulation and refinement continued through the year, and the finished processor design was handed to HP’s software developers in July 1984.

Announcement and first machines

HP Precision Architecture — the name PA-RISC came into wide use somewhat later, once “RISC” had become the industry’s preferred label — was announced on 26 February 1986. Two systems launched with it simultaneously: the HP 3000 Series 930, extending HP’s older MPE business-computing line onto the new architecture, and the HP 9000 Model 840, the first PA-RISC Unix machine. Both used the same first-generation hardware implementation, code-named TS-1: a discrete design built from 74F-series TTL logic spread across several circuit boards (accounts vary between five and six), reflecting how new the technology still was. The HP 9000 Model 840 reportedly began shipping to customers around November 1986. The first confirmed single-chip CMOS implementation, PCX (also known internally as CMOS26B), followed in 1990 — the first PA-RISC processor small enough to fit on one die.

The Language

Registers

PA-RISC 1.0 and 1.1 define thirty-two 32-bit general registers, GR0 through GR31 (GR0 is hardwired to zero), with several given architectural roles by the calling convention rather than by the hardware itself:

PA-RISC 1.0 also defines sixteen 64-bit floating-point registers; PA-RISC 1.1 doubles that to thirty-two, and the same physical registers can be addressed as sixty-four 32-bit halves or sixteen 128-bit quad registers. PA-RISC 2.0 widens the general registers themselves to 64 bits. Seven of the general registers — GR1, GR8, GR9, GR16, GR17, GR24 and GR25 — are also designated shadow registers, which exist purely to speed interrupt handling by letting the processor save their values without an explicit store. These are distinct from the eight space registers (SR0–SR7), which hold address-space identifiers rather than shadowed general-register state — a naming collision (“SR” for both) that is easy to conflate.

Completers: the architecture’s signature idiom

Rather than give load, store, arithmetic and branch instructions separate mnemonics for each variant, PA-RISC attaches a comma-separated completer to the base mnemonic. A handful of examples:

The ,N completer that appears on branches is tied to PA-RISC’s nullification mechanism: almost any instruction can conditionally suppress (“nullify”) the effect of the instruction that follows it, which is how the architecture gets branch-delay-slot behavior and conditional execution without a separate predicate-register facility. A taken branch with ,N set nullifies its own delay-slot instruction instead of executing it — the opposite of the usual MIPS/SPARC convention where the delay slot always executes.

Addressing and pseudo-operations

Memory operands are written displacement(base), and the assembler recognizes common shorthand forms as pseudo-operations that expand to a real instruction: COPY r1,r2 assembles to OR r1,0,r2, and LDI value,r assembles to LDO value(0),r. Unlike CISC addressing, PA-RISC has no scaled-index mode that multiplies an index register by an operand’s size — array indexing has to compute the byte offset explicitly, which is a direct consequence of keeping every instruction a single, fixed 32-bit word.

Instruction set size

PA-RISC 1.0 defines about 140 instructions; PA-RISC 1.1 grows that to roughly 190, mostly through expanded floating-point and multimedia operations. That is more than many contemporary RISC designs, a consequence of PA-RISC’s compiler-target philosophy: HP’s design notes describe the set as tuned so that simple, frequently used operations execute in a single cycle, while a smaller number of multi-cycle instructions exist specifically to support languages such as COBOL and FORTRAN that the HP 3000 and HP 9000 lines needed to keep running.

Code Example

A minimal HP-UX procedure

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        .code
        .export main,entry
main
        .proc
        .callinfo frame=64,calls,save_rp
        .entry
        stw     rp,-20(sp)      ; save return pointer into the caller's frame
        ldo     64(sp),sp       ; extend the stack frame

        ldi     42,ret0         ; ret0 (gr28) := 42

        ldw     -84(sp),rp      ; restore return pointer
        bv,n    r0(rp)          ; branch to return address, nullifying the delay slot
        .exit
        .procend

The ,MA/,MB completers mean the same effect can often be reached without a separate LDO adjusting the stack pointer — STW,MA rp,64(sp) both stores and advances the frame in one instruction, which is the pattern real HP-UX-generated prologues use.

Evolution

The architecture moved from TTL boards (TS-1, 1986) to single-chip CMOS (PCX, 1990), then through a long run of PA-7000-series 32-bit implementations: PA-7000 (1991, the first PA-RISC 1.1 part), PA-7100, the multimedia-capable PA-7100LC, which introduced HP’s first MAX SIMD extension in January 1994, and the superscalar PA-7200, which shipped in early 1995. PA-RISC 2.0, announced with the PA-8000 in January 1996, doubled the architecture to 64 bits, added out-of-order execution and a wider MAX-2 extension, and carried the line through the PA-8200, PA-8500, PA-8600, PA-8700 and finally the dual-core PA-8800 and PA-8900 of the mid-2000s. Through most of that run PA-RISC leaned on large on-chip level-one caches rather than off-chip level-two cache — only the low-cost PA-7100LC and PA-7300LC parts added one.

By the late 1990s HP had already committed the architecture’s future to Itanium, the 64-bit design jointly developed with Intel as PA-RISC’s successor. HP stopped selling new PA-RISC-based HP 9000 systems at the end of 2008 and closed out standard server support in 2013.

Current Relevance

PA-RISC production hardware is gone, but the toolchain around the assembly language has not fully followed it:

• GNU binutils still assembles and links hppa object code, and the Linux kernel’s parisc port is actively maintained upstream, still building against current kernel releases.
• GCC dropped its 32-bit hppa*-hpux10/hppa*-hpux11 targets in GCC 13 (2023); the hppa-linux target and the 64-bit hppa64-hp-hpux11 configuration continue to be supported.
• Debian’s hppa port shipped as an officially supported architecture from woody (2002) through squeeze, then moved to the community-run Debian Ports project after being dropped as a release architecture following the squeeze (2011) cycle; Debian Ports has kept it building.
• Emulation and documentation. HP’s own PA-RISC 1.1 Architecture and Instruction Set Reference Manual and related documents remain in wide circulation, and sites such as OpenPA.net catalog the processor family and surviving systems in detail for a platform that otherwise survives mainly in private collections.

Why It Matters

PA-RISC’s real legacy is less any one clever instruction than the discipline behind the whole design: keep the instruction set an easy compiler target, keep most operations single-cycle, and push complexity into a small, well-defined set of completers and pseudo-operations rather than into a sprawling opcode space. That approach let one architecture span HP’s MPE business systems and its HP-UX technical workstations and servers for over two decades, scale from six-board TTL implementations to dual-core 64-bit chips, and carry compiler-generated code from COBOL and FORTRAN through to C and Fortran-90 with barely a change in the underlying instruction set’s shape. It was also, in the end, a design HP judged not worth carrying forward on its own: the joint HP/Intel decision to build Itanium as PA-RISC’s successor set the architecture’s ceiling years before the last PA-8900-based server shipped, which is why PA-RISC is remembered today as a well-engineered RISC family that ran out of runway rather than one that failed on its own terms.